Silicon architectures for neural nets : proceedings of the IFIP WG 10.5 Workshop on Silicon Architectures for Neural Nets, Saint Paul de Vence, France, 28-30 November, 1990
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| 049 | 1 | ▼l 421106300 ▼f 과학 |
| 050 | 0 0 | ▼a QA76.87 ▼b .I38 1990 |
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| 111 | 2 | ▼a IFIP WG 10.5 Workshop on Silicon Architectures for Neural Nets ▼c (1990 : ▼d Saint-Paul, Alpes Maritimes, France) |
| 245 | 1 0 | ▼a Silicon architectures for neural nets : ▼b proceedings of the IFIP WG 10.5 Workshop on Silicon Architectures for Neural Nets, Saint Paul de Vence, France, 28-30 November, 1990 / ▼c edited by Mariagiovanna Sami, Jesus Calzadilla-Daguerre. |
| 260 | ▼a Amsterdam ; ▼a New York : ▼b North-Holland ; ▼a New York, N.Y., U.S.A. : ▼b Distributors for the U.S. and Canada, Elsevier Science Pub., ▼c 1991. | |
| 300 | ▼a ix, 304 p. : ▼b ill. ; ▼c 24 cm. | |
| 504 | ▼a Includes bibliographical references. | |
| 650 | 0 | ▼a Neural networks (Computer science) ▼x Congresses. |
| 650 | 0 | ▼a Computer architecture ▼x Congresses. |
| 650 | 0 | ▼a Silicon ▼x Congresses. |
| 653 | 0 | ▼a Computers ▼a Integrated circuits ▼a Design |
| 700 | 1 0 | ▼a Sami, Mariagiovanna. |
| 700 | 2 0 | ▼a Calzadilla-Daguerre, Jes？s. |
소장정보
| No. | 소장처 | 청구기호 | 등록번호 | 도서상태 | 반납예정일 | 예약 | 서비스 |
|---|---|---|---|---|---|---|---|
| No. 1 | 소장처 과학도서관/Sci-Info(2층서고)/ | 청구기호 006.3 I23s | 등록번호 121163046 | 도서상태 대출가능 | 반납예정일 | 예약 | 서비스 |
| No. 2 | 소장처 과학도서관/Sci-Info(2층서고)/ | 청구기호 006.3 I23s | 등록번호 421106300 | 도서상태 대출가능 | 반납예정일 | 예약 | 서비스 |
컨텐츠정보
목차
CONTENTS Neural networks: perspectives from UNISYS = 1 Distributed large neural networks on silicon = 11 An application oriented development environment for neural net models on multiprocessor EMMA-2 = 31 Comparing digital neural network architectures = 45 Computing with very large numbers of elements = 65 Neural network emulation on polymorphic processor arrays = 79 An artificial neural net based on a ring archtecture = 89 Neural network clock distribution = 101 A CMOS analog architecture for adaptive neural networks = 113 Floating gates as adaptive weights for artificial neural networks = 125 A proposal for neural macrocell array = 137 Radix-r implementation of neural nets = 153 Towards a general-purpose neurocomputing system = 167 Wafer scale intergration for the implementation of artificial neural networks = 179 An intelligent sensor integrated VLSI preprocessor/emulator facillity for neural networks = 187 Better activation functions for back-propagation training = 201 The algorithmic basis of neurocomputer design = 207 HiPNet-1: A highly pipelined architecture for neural network training = 217 Dual computing structures containing analog cellular neural networks and digital decision units = 233 VLSI design of a neural signal processor = 245 Design and implementation of a dedicated neural network = 261 Potential performance advantaged of delay insensitivity = 271 Mapping of neural networks specific architectures onto th non-planar chip surfaces = 283