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FPGA implementations of neural networks

FPGA implementations of neural networks (2회 대출)

자료유형
단행본
개인저자
Ormondi, A. R Rajapakse, Jagath Chandana
서명 / 저자사항
FPGA implementations of neural networks / edited by A.R. Omondi, J.C. Rajapakse.
발행사항
New York ;   London :   Springer ,   2005.  
형태사항
xii, 360 p. : ill. ; 25 cm.
ISBN
0387284850 (hbk.)
서지주기
Includes bibliographical references.
일반주제명
Neural networks (Computer science) Field programmable gate arrays.
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245 0 0 ▼a FPGA implementations of neural networks / ▼c edited by A.R. Omondi, J.C. Rajapakse.
260 ▼a New York ; ▼a London : ▼b Springer , ▼c 2005.
300 ▼a xii, 360 p. : ▼b ill. ; ▼c 25 cm.
504 ▼a Includes bibliographical references.
650 0 ▼a Neural networks (Computer science)
650 0 ▼a Field programmable gate arrays.
700 1 ▼a Ormondi, A. R
700 1 ▼a Rajapakse, Jagath Chandana

소장정보

No. 소장처 청구기호 등록번호 도서상태 반납예정일 예약 서비스
No. 1 소장처 세종학술정보원/과학기술실(5층)/ 청구기호 006.32 F796 등록번호 151217063 (2회 대출) 도서상태 대출가능 반납예정일 예약 서비스 B M ?

컨텐츠정보

책소개

During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.

During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.


정보제공 : Aladin

목차

Preface. 1. FPGA Neurocomputers; A.R.Omondi, J.C.Rajapakse and M.Bajger. 2. Arithmetic precision for BP networks; M.Moussa, S.Areibi and K.Nichols. 3. FPNA: Concepts and properties; B.Girau . 4. FPNA: Applications and implementations; B.Girau . 5. Back-Propagation Algorithms Achieving 5 GOPS on the VirtexE; K.Paul and S.Rajopadhye . 6. FPGA Implementation of Very Large Associative Memories; D.Hammerstrom, C.Gao, S.Zhu and M.Butts . 7. FPGA Implementations of Neocognitrons; A.Noriaki Ide and J.Hiroki Saito . 8. Self Organizing Feature Map for Color Quantization on FPGA; C-H.Chang, M.Shibu and R.Xiao . 9. Implemention of Self-Organizing Feature Maps in Reconfigurable Hardware; M.Porrmann, U.Witkowski and U.Ruckert . 10. FPGA Implementation of a Fully and Partially Connected MLP; A.Canas, E.M.Ortigosa, E.Ros and P.M.Ortigosa . 11. FPGA Implementation of Non-Linear Predictors; R.Gadea-Girones and A.Ramrez-Agundis . 12. The REMAP Reconfigurable Architecture: a retrospective; L.Bengtsson, A.Linde, T.Nordstrom, B.Svensson and M.Taveniku .


정보제공 : Aladin

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