| 000 | 00000cam u2200205 a 4500 | |
| 001 | 000045970585 | |
| 005 | 20190214140430 | |
| 008 | 190212s2017 ne a b 001 0 eng d | |
| 015 | ▼a GBB705244 ▼2 bnb | |
| 020 | ▼a 9781785480966 (hbk.) | |
| 020 | ▼z 9780081011966 (ebk.) | |
| 035 | ▼a (KERIS)BIB000014663877 | |
| 040 | ▼a 221016 ▼b 221016 ▼c 221016 ▼d 211009 | |
| 082 | 0 4 | ▼a 621.38152 ▼2 23 |
| 084 | ▼a 621.38152 ▼2 DDCK | |
| 090 | ▼a 621.38152 ▼b P7152 | |
| 245 | 0 0 | ▼a Plasma etching processes for CMOS devices realization / ▼c edited by Nicolas Posseme. |
| 260 | ▼a Amsterdam : ▼b Elsevier, ▼c c2017. | |
| 300 | ▼a x, 121 p. : ▼b ill. ; ▼c 24 cm. | |
| 490 | 1 | ▼a Electronics engineering series |
| 504 | ▼a Includes bibliographical references and index. | |
| 650 | 0 | ▼a Metal oxide semiconductors, Complementary ▼x Design and construction. |
| 650 | 0 | ▼a Plasma etching. |
| 700 | 1 | ▼a Posseme, Nicolas. |
| 830 | 0 | ▼a Electronics engineering series. |
| 945 | ▼a KLPA |
소장정보
| No. | 소장처 | 청구기호 | 등록번호 | 도서상태 | 반납예정일 | 예약 | 서비스 |
|---|---|---|---|---|---|---|---|
| No. 1 | 소장처 과학도서관/Sci-Info(2층서고)/ | 청구기호 621.38152 P7152 | 등록번호 121247871 (1회 대출) | 도서상태 대출가능 | 반납예정일 | 예약 | 서비스 |
컨텐츠정보
책소개
Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent. Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography. This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization.
Feature
- Helps readers discover the master technology used to pattern complex structures involving various materials
- Explores the capabilities of cold plasmas to generate well controlled etched profiles and high etch selectivities between materials
- Teaches users how etch compensation helps to create devices that are smaller than 20 nm
정보제공 :
목차
Front Cover -- Plasma Etching Processes for CMOS Device Realization -- Copyright -- Contents -- Preface -- 1 CMOS Devices Through the Years -- 1.1. Scaling law by Dennard -- 1.2. CMOS device improvement through the years -- 1.3. Summary -- 1.4. What is coming next? -- 1.5. Bibliography -- 2 Plasma Etching in Microelectronics -- 2.1. Overview of plasmas and plasma etch tools -- 2.2. Plasma surface interactions during plasma etching -- 2.3. Patterns transfer by plasma etching -- 2.4. Conclusion -- 2.5. Bibliography -- 3 Patterning Challenges in Microelectronics -- 3.1. Optical immersion lithography -- 3.2. Next-generation lithography -- 3.3. Coclusion -- 3.4. Bibliography -- 4 Plasma Etch Challenges for Gate Patterning -- 4.1. pSi gate etching -- 4.2. Metal gate etching -- 4.3. Stopping on the gate oxide -- 4.4. High-k dielectric etching -- 4.5. Line width roughness transfer during gate patterning -- 4.6. Chamber wall consideration after gate patterning -- 4.7. Summary -- 4.8. Bibliography -- List of Acronyms -- List of Authors -- Index -- Back Cover -- .